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SI9135
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Vishay Siliconix
SI9135
SMBus Multi-Output Power-Supply Controller
FEATURES
* * * * * * * * Up to 95% Efficiency 3% Total Regulation (Each Controller) 5.5-V to 30-V Input Voltage Range 3.3-V, 5-V, and 12-V Outputs 200-kHz/300-kHz Low-Noise Frequency Operation Precision 3.3-V Reference Output 30 mA Linear Regulator Output SMBUS Interface * High Efficiency Pulse Skipping Mode Operation at Light Load * Only Three Inductors Required*No Transformer * LITTLE FOOT(R) Optimized Output Drivers * Internal Soft-Start * Synchronizable * Minimal External Control Components * 28-Pin SSOP Package
DESCRIPTION
The SI9135 is a current-mode PWM and PSM converter controller, with two synchronous buck converters (3.3 V and 5 V) and a flyback (non-isolated buck-boost) converter (12 V). Designed for portable devices, it offers a total five power outputs (three tightly regulated dc/dc converter outputs, a precision 3.3-V reference and a 5-V LDO output). It requires minimum external components and is capable of achieving conversion efficiencies approaching 95%. Along with the SMBUS interface, the SI9135 provides programmable output selection capability. The SI9135 is available in a 28-pin SSOP package and specified to operate over the extended commercial (0C to 90C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
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S-60752--Rev. B, 05-Apr-99 1
SI9135
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ABSOLUTE MAXIMUM RATINGS
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36 V PGND to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V VL to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5 V BST3, BST5, BSTFY to GND . . . . . . . . . . . . . . . . . . . -0.3 V to +36 V VL Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous LX3 to BST3; LX5 to BST5; LXFY to BST . . . . . . . . . . . -6.5 V to 0.3 V Inputs/Outputs to GND (SYNC, CS3, CS5, CSP, CSN) . . . . . . . . . . . . . . -0.3 V to (VL +0.3 V) SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V DL3, DL5, DLFY to PGND . . . . . . . . . . . . . . . . . -0.3 V to (VL +0.3 V) DH3 to LX3, DH5 to LX5, DHFY to LXFY . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (BSTX +0.3 V) Continuous Power Dissipation (TA = 90C)a 28-Pin SSOPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 mW Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . 0C to 90C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . -40C to 125C Lead Temperature (Soldering, 10 Sec.) . . . . . . . . . . . . . . . . . . . 300C Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 9.52 mW/C above 90C.
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Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
Test Conditions Parameter 3.3-V Buck Controller
Total Regulation (Line, Load, and Temperature) Line Regulation Load Regulation Current Limit Bandwidth Phase Margin VIN = 6 to 30 V, 0 < VCS3 - VFB3 < 90 mV VIN = 6 to 30 V 0 < VCS3 - VFB3 < 90 mV VCS3 - VFB3 L = 10 H, C = 330 F RSENSE = 20 m 90 125 50 65 3.23 3.33 3.43 0.5 0.5 160 V % mV kHz VIN = 15 V , IVL = IREF = 0 mA TA = 0C to 90C, All Converters ON
Limits Mina Typb Maxa Unit
5-V Buck Controller
Total Regulation (Line, Load, and Temperature) Line Regulation Load Regulation Current Limit Bandwidth Phase Margin VIN = 6 to 30 V, 0 < VCS5 - VFB5 < 90 mV VIN = 6 to 30 V 0 < VCS5 - VFB5 < 90 mV VCS5 - VFB5 L = 10 H, C = 330 F RSENSE = 20 m 90 125 50 65 4.88 5.03 5.18 0.5 0.5 160 V % mV kHz
12-V Flyback Controller
Total Regulation (Line, Load, and Temperature) Line Regulation Load Regulation Current Limit Bandwidth Phase Margin VIN = 6 to 30 V, 0 < VCSP - VCSN < 300 mV VIN = 6 to 30 V 0 < VCSP - VFBN < 300 mV VCSP - VCSN L = 10 H, C = 100 F RSENSE = 100 m, Ccomp = 120 pF 330 410 10 65 11.4 12.0 12.6 0.5 0.5 500 V % mV kHz
Internal Regulator
VL Output VL Fault Lockout Voltage VL Fault Lockout Hysteresis VL /FB5 Switchover Voltage VL /FB5 Switchover Hysteresis S-60752--Rev. B, 05-Apr-99 2 4.2 75 All Converters OFF, VIN >5.5 V, 0 FaxBack 408-970-5600, request 70817 www.siliconix.com
SI9135
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SPECIFICATIONS
Test Conditions Parameter Reference
REF Output REF Load Regulation No External Load 0 to 1 mA 3.24 3.30 30 3.36 75 V mV VIN = 15 V , IVL = IREF = 0 mA TA = 0C to 90C, All Converters ON
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Limits Mina Typb Maxa Unit
Supply Current
Supply Current-Shutdown Supply Current-Operation All Converters OFF, No Load All Converters ON, No Load, FOCS = 200 kHz 35 1100 60 1800 A
Oscillator
Oscillator Frequency SYNC High-Pulse Width SYNC Low-Pulse Width SYNC Rise/Fall Range SYNC VIL SYNC VIH Oscillator SYNC Range Maximum Duty Cycle SYNC tied to GND or VL SYNC tied to REF VL - 0.5 250 92 89 95 92 400 SYNC tied to REF SYNC tied to GND or VL 270 180 200 200 200 0.8 V kHz % nsec 300 200 330 220 kHz
Outputs
Gate Driver Sink/Source Current (Buck) Gate Driver On-Resistance (Buck) Gate Driver Sink/Source Current (Flyback) Gate Driver On-Resistance (Flyback) DL3, DH3, DL5, DH5 Forced to 2 V High or Low DHFY, DLFY Forced to 2 V High or Low 1 2 0.2 15 7 A A
SCL, SDA
VIL VIH Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. 1.4 0.6 V
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S-60752--Rev. B, 05-Apr-99 3
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PIN CONFIGURATION ORDERING INFORMATION
Part Number
SI9135LG
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Temperature Range
0 to 90C
VOUT
3.3 V, 5 V, 12 V
PIN DESCRIPTION
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Symbol
CS3 FBFY BSTFY DHFY LXFY DLFY CSP CSN GND COMP REF SYNC SCL SDA CS5 DH5 LX5 BST5 DL5 PGND FB5 VL VIN DL3 BST3 LX3 DH3 FB3 Current sense input for 3.3-V buck. Feedback for flyback.
Description
Boost capacitor connection for flyback converter. Gate-drive output for flyback high-side MOSFET. Inductor connection for flyback converter. Gate-drive output for flyback low-side MOSFET. Current sense positive input for flyback converter. Current sense negative input for flyback converter. Analog ground. Flyback compensation connection, if required. 3.3-V internal reference. Oscillator synchronization inputs. SMBUS clock line. SMBUS data line. Current sense input for 5-V buck controller. Inductor connection for buck 5-V. Gate-drive output for 5-V buck high-side MOSFET. Boost capacitor connection for 5-V buck converter. Gate-drive output for 5-V buck low-side MOSFET. Power ground. Feedback for 5-V buck. 5-V logic supply voltage for internal circuitry. Input voltage Gate-drive output for 3.3-V buck low-side MOSFET. Boost capacitor connection for 3.3-V buck converter. Inductor connection for 3.3-V buck low-side MOSFET. Gate-drive output for 3.3-V buck high-side MOSFET. Feedback for 3.3-V buck.
S-60752--Rev. B, 05-Apr-99 4
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SI9135
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TYPICAL CHARACTERISTICS (25C UNLESS OTHERWISE NOTED)
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S-60752--Rev. B, 05-Apr-99 5
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TYPICAL WAVEFORMS
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S-60752--Rev. B, 05-Apr-99 6
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SI9135
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TYPICAL WAVEFORMS
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S-60752--Rev. B, 05-Apr-99 7
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STANDARD APPLICATION CIRCUIT
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FIGURE 1.
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SMBUS Specification SMBus: The System Management Bus is a two-wire interface through which simple power related chips can communicate with the rest of the system. It uses I2C as its backbone. Both SDA and SCL are bidirectional lines, connected to a positive voltage via a pull-up resistor. When the bus is free, both lines
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are high. The output stages of devices connected to the bus must have an open drain or open collector in order to perform the wired AND function. Data on the SMBus can be transferred at a clock rate up to 100 kHz. SI9135 is a slave with SMBus address of 0110000.
SMBUS TRUTH TABLE
State
Shutdown Buck3 On Buck5 On Flyback On Buck3, Buck5 On Buck3, Flyback On Buck5, Flyback on All On Notes a. Positive logic level is used b. X: don't care
D7
0 1 0 0 1 1 0 1
D6
0 0 1 0 1 0 1 1
D5
0 0 0 1 0 1 1 1
D4
X X X X X X X X
D3
X X X X X X X X
D2
X X X X X X X X
D1
X X X X X X X X
D0
X X X X X X X X
SMBUS ELECTRICAL SPECIFICATION (Test Conditions: V+ = 5.5 to 30 V, TA = OC)
Symbol
VIL VIH VOL ILEAK
Parameter
Data, Clock Input Low Voltage Data, Clock Input High Voltage Data, Clock Output Low Voltage Input Leakage
Min
-0.5 1.4
Max
0.6 5.5 0.4 1
Units
V
A
SMBUS AC SPECIFICATIONS
Symbol
FSMB TBUF THD TSU TLOW THIGH TF TR
Parameter
SMBus Operation Frequency Bus free time between Stop and Start Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/Data Fall Time Clock/Data Rise Time
Min
10 4.7 300 250 4.7 4.0
Max
100
Units
kHz s ns
50 300 1000
s
ns
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S-60752--Rev. B, 05-Apr-99 9
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TIMING DIAGRAMS
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FIGURE 2. Start-Up Timing Sequence
S-60752--Rev. B, 05-Apr-99 10
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DETAILED FUNCTIONAL BLOCK DIAGRAM
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FIGURE 3. Buck Block Diagram
FIGURE 4. PWM Flyback Block Diagram
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S-60752--Rev. B, 05-Apr-99 11
SI9135
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DETAILED FUNCTIONAL BLOCK DIAGRAM
FIGURE 5. Complete SI9135 Block Diagram
DESCRIPTION OF OPERATION
Start-up Sequence SI9135 is normally controlled by its SMBus interface after VIN is applied. Initially, if there is no incoming SMBus control command, it comes up in its default power on sequence, first the LDO 5 V will come up within its tolerance, and then the precision 3.3-V reference will come up. Immediately afterwards, the oscillator will begin and 3.3-V BUCK converter will turn on and then 5-V BUCK converter and at last 12-V FLYBACK converter. If SI9135 receives any SMBus controlling command after LDO 5 V is established, the designated converters will be allowed to turn on or off independently depending on the command received. In the event of all three converters are turned off, the oscillator will be turned off, the total system would only draw 35-A supply current. Each converter can soft-start separately. The integrated internal soft-start circuitry for each converter gradually increases the inductor maximum peak current during softstart period (approximately 4 msec), preventing excessive currents being drawn from the input during startup. The softstart is controlled by initial default start up sequence or incoming SMBus command. SI9135 converters a 5.5-V to 30-V input voltage to five outputs, two BUCK (step-down) high current, PWM, switchmode supplies, one at 3.3 V and one at 5 V, one FLYBACK 12-V PWM switch-mode supply, one precision 3.3-V reference and one 5-V Low Drop Out linear regulator output. Switchmode supply output current capabilities depend on external components (can exceed 10 A). With typical application shown on the application diagram, the two BUCK converters deliver 4 A and the FLYBACK converters deliver 0.25 A. The recommended load current for precision 3.3-V reference output is less than 1 mA, the recommended load current for 5-V LDO output current is less than 30 mA. In order to maximize the power efficiency, when the 5-V BUCK converter supply is above 4.5 V, the BUCK converter's output is internal connected to LDO output. Buck Converter Operation The 3.3-V and 5-V buck converters are both current-mode PWM and PSM (during light load operation) regulators using high-side bootstrap n-channel and low-side n-channel MOSFETs. At light load conditions, the converters switch at a lower frequency than the clock frequency, seen like some clock pulses between the actual switching are skipped, this operating condition is defined as pulse-skipping. The operation of the converter(s) switching at clock frequency is defined as normal operation.
S-60752--Rev. B, 05-Apr-99 12
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Normal Operation: Buck Converters In normal operation, the buck converter high-side MOSFET is turned on with a delay (known as break-before-make time tBBM), after the rising edge of the clock. After a certain on time, the high-side MOSFET is turned off and then after a delay (tBBM), the low-side MOSFET is turned on until the next rising edge of the clock, or the inductor current reaches zero. The tBBM (approximately 25 ns to 60 ns), has been optimized to guarantee the efficiency is not adversely affected at the high switching frequency and a specified minimum to account for variations of possible MOSFET gate capacitances. During the normal operation, the high-side MOSFET switch on-time is controlled internally to provide excellent line and load regulation over temperature. Both buck converters should have load, line, regulation to within 0.5% tolerance. Pulse Skipping: Buck Converters When the buck converter switching frequency is less than the internal clock frequency, its operation mode is defined as pulse skipping mode. During this mode, the high-side MOSFET is turned on until VCS-VFB reaches 20 mV, or the on time reaches its maximum duty ratio. After the high-side MOSFET is turned off, the low-side MOSFET is turned on after the tBBM delay, which will remain on until the inductor current reaches zero. The output voltage will rise slightly above the regulation voltage after this sequence, causing the controller to stay idle for the next one, or several clock cycles. When the output voltage falls slightly below the regulation level, the high-side MOSFET will be turned on again at the next clock cycle. With the converter remaining idle during some clock cycles, the switching losses are reduced in order to preserve conversion efficiency during the light output current condition. Current Limit: Buck Converters When the buck converter inductor current is too high, the voltage across pin CS3(5) and pin FB3(5) exceeds approximately 120 mV, the high-side MOSFET would be turned off instantaneously regardless of the input, or output condition. The SI9135 features clock cycle by clock cycle current limiting capability. Flyback Converter Operation Designed mainly for PCMCIA or EEPROM programming, the SI9135 has a 12-V output non-isolated buck boost converter, called for brevity a flyback. It consists of two n-channel MOSFET switches that are turned on and off in phase, and two diodes. Similar to the buck converter, during the light load conditions, the flyback converter will switch at a frequency lower than the internal clock frequency, which can be defined as pulse skipping mode (PSM); otherwise, it is operating in normal PWM mode.
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Normal Operation: Flyback Converter In normal operation mode, the two MOSFETs are turned on at the rising edge of the clock, and then turned off. The on time is controlled internally to provide excellent load, line, and temperature regulation. The flyback converter has load, line and temperature regulation well within 0.5%. Pulse Skipping: Flyback Converter Under the light load conditions, similar to the buck converter, the flyback converter will enter pulse skipping mode. The MOSFETs will be turned on until the inductor current increases to such a level that the voltage across the pin CSP and pin CSN reaches 100 mV, or the on time reaches the maximum duty cycle. After the MOSFETs are turned off, the inductor current will conduct through two diodes until it reaches zero. At this point, the flyback converter output will rise slightly above the regulation level, and the converter will stay idle for one or several clock cycle(s) until the output falls back slightly below the regulation level. The switching losses are reduced by skipping pulses and so the efficiency during light load is preserved. Current Limit: Flyback Converter Similar to the buck converter; when the voltage across pin CSP and pin CSN exceeds 410-mV typical, the two MOSFETs will be turned off regardless of the input and output conditions. SMBus Commands After completion of startup, SI9135's converters can be individually or as a group commanded on or off using a code word on the SMBus, as detailed in the SMBus Truth Table. The command sequence is: A. Receive a start bit, which is a falling edge on the SDA line while the SCL line is high. B. Receive a one-byte address, which for SI9135 is 01100000. C. Send an acknowledge bit. D. Receive a one-byte command. E. Send an acknowledge bit. F. Receive a stop bit, which is a rising edge on the SDA line while the SCL line is high. This is a total of 20 bits, which at the maximum clock frequency of 100 kHz translates into 200 sec before any change in the status of SI9135 ban be accomplished. If SI9135 receives a command to turn on (respectively, off) a converter that is already on (respectively, off) it shall not falsely command the converter off (respectively, on). SI9135 must be able to receive a stop command at any time during a command sequence. If SI9135 receives a stop command during a command sequence, it must not change the state of any converter, and must be ready to receive the next command sequence.
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Grounding There are two separate grounds on the SI9135, analog signal ground (GND) and power ground (PGND). The purpose of two separate grounds is to prevent the high currents on the power devices (both external and internal) from interfering with the analog signals. The internal components of SI9135 have their grounds tied (internally) together. These two grounds are then tied together (externally) at a single point, to ensure SI9135 noise immunity. This separation of grounds should be maintained in the external circuitry, with the power ground of all power devices being returned directly to the input capacitors, and the small signal ground being returned to the GND pin of SI9135. ON/OFF Function Logic-low shuts off the appropriate section by disabling the gate drive stage. High-side and low-side gate drivers are turned off when ON/OFF pins are logic-low. Logic-high enables the DH and DL pins. Stability
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efficiency. The converters are current mode control, with a bandwidth substantially higher than the LC tank dominant pole frequency of the output filter. To ensure stability, the minimum capacitance and maximum ESR values are:
V REF C LOAD -----------------------------------------------------------2 x V OUT x R CS x BW V OUT x R CS ESR ------------------------------VREF
Where VREF = 3.3 V, VOUT is the output voltage (5 V or 3.3 V), Rcs is the current sensing resistor in ohms and BW = 50 khz With the components specified in the application circuit (L = 10 H, RCS = 0.02 , COUT = 330 F, ESR approximately 0.1 ), the converter should have a bandwidth at approximately 50 kHz, with minimum phase margin of 65, and dc gain above 50 dB.
Other Outputs
The SI9135 also provides a 3.3-V reference which can be external loaded up to 1 mA, as well as, a 5-V LDO output which can be loaded 30 mA, or even more depending on the system application. When the 5-V buck converter is turned on, the 5-V LDO output is shorted with the 5-V buck converter output, so its loading capability is substantially increased. For stability, the 3.3-V reference output requires a 1-F capacitor, and 5-V LDO output requires a 4.7-F capacitor.
Buck Converters
In order to simplify designs, the SI9135 requires no specified external components except load capacitors for stability control. Meanwhile, it achieves excellent regulation and
S-60752--Rev. B, 05-Apr-99 14
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